In the semiconductor production industry, various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include the deposition of layers of different materials including metallization layers, passivation layers and insulation layers on the wafer substrate, as well as photoresist stripping and sidewall passivation polymer layer removal. In modern memory devices, for example, multiple layers of metal conductors are required for providing a multi-layer metal interconnection structure in defining a circuit on the wafer. Chemical vapor deposition (CVD) processes are widely used to form layers of materials on a semiconductor wafer. Other processing steps in the fabrication of the circuits include formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby leaving the metal layer in the form of the masked pattern; removing the mask layer using reactive plasma and chlorine gas, thereby exposing the top surface of the metal interconnect layer; cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate; and removing or stripping polymer residues from the wafer substrate.
After the devices are fabricated on the wafer surface, the wafers may be transported to a separate facility which is remote from the fabrication facility for packaging or other processing. The integrated circuits on the wafer are prone to damage due to mechanical shock during transit from the fabrication facility to the packaging or other facility. In addition to mechanical shock, integrated circuits are susceptible to damage by electrostatic discharges (ESD) and electrical overstress (EOS). As USLI technology continues downscaling of device features, the wafer size becomes correspondingly larger for economical production of the integrated circuits. Accordingly, the wafers become increasingly expensive with increased size. For example, the cost of a 12″ wafer is about 2.5 times the cost of an 8″ wafer. One production lot (25 wafers) of 8″ wafers costs about $40,000. Thus, protection of the wafers during shipping is of utmost importance.
One of the last processes in the production of semiconductor integrated circuits (IC) is multi-leveled packaging, which includes expanding the electrode pitch of the IC chips containing the circuits for subsequent levels of packaging; protecting the chip from mechanical and environmental stress; providing proper thermal paths for channeling heat dissipated by the chip; and forming electronic interconnections. The manner in which the IC chips are packaged dictates the overall cost, performance, and reliability of the packaged chips, as well as of the system in which the package is applied.
Before they are used as electronic components in electronic appliances such as cell phones, computer processors and the like, the IC chips or die are separated from each other in the wafer and removed from the wafer for higher-order packaging. This die separation step is typically accomplished using a diamond-bladed saw, which cuts the wafer material between dies along multiple parallel X-axis scribe lines and multiple parallel Y-axis scribe lines in the wafer surface. Accordingly, the intact or uncut wafers having the die fabricated thereon are first removed from a wafer cassette and placed on an adhesive tape that is secured to a rigid support frame. The adhesive tape serves to secure the die to the support frame once the silicon wafer material is severed along the scribe lines between adjacent die. A diamond-blade dicing saw is used to cut the wafer along the X-axis and Y-axis scribe lines, to separate the adjacent die from each other. As the die are diced from the wafer, a DI water spray is used to remove silicon slurry residue generated by the saw. After the dicing process, the adhesive tape may be cured by UV radiation to attenuate the adhesive strength of the tape. Finally, the multiple die, severed from each other and from the wafer, are lifted from the adhesive tape.
As shown in FIG. 1, in the conventional die-separating process, the diamond-studded saw blade 18 cuts a separation channel 14 completely through the silicon wafer material of a wafer 10, between each die 20 and along the scribe lines 12 inscribed on the surface of the wafer 10. Each separation channel 14 cut by the saw blade 18 extends typically about halfway through the thickness of the adhesive tape 16, leaving the lower half thickness of the tape 16 to secure the separated die 20 together on the support frame. Accordingly, particularly for small die (˜10 mm or less thickness) which are characteristic of advanced IC fabrication processes, there remains no silicon wafer material and an inadequate thickness of adhesive tape between adjacent die to absorb much of the vibration imparted by the saw blade as the blade cuts along the remaining scribe lines separating each die from the adjacent die. Consequently, as shown in FIG. 2, the saw-induced vibration which accompanies the conventional method of cutting the entire thickness of the wafer material and half of the thickness of the adhesive tape beneath the scribe lines between the die frequently forms chips 22 in the top and backside edges of the die, as well as cracks 24 in the die 24, during the dicing process. The chips and cracks are typically most abundant along the side of the die which is the last to be severed from the wafer.
Several approaches have been taken to ameliorate the vibration-induced chipping and cracking of IC dies during the die separation process. One of these includes the use of a high-strength adhesion tape to bind the wafer to the support frame and to absorb vibrational energy during dicing, followed by UV curing of the tape prior to lifting the separated die from the tape. However, this process contributes excessive overall cost to the die separation process. Another approach includes the use of high-strength adhesive tape to bind the wafer, followed by the use of a saw blade designed for cutting thin wafers in order to reduce vibration during dicing. While reducing the formation of vibration-induced cracks and chips in the die during the die separation step, this process leads to cracking and chipping of the die as the separated die are subsequently lifted from the tape. Accordingly, a new and improved process is needed for separating die on a wafer in order to prevent cracking and/or chipping of the die due to excessive vibrational energy imparted by a wafer-dicing saw.
Accordingly, an object of the present invention is to provide a new and improved method for separating die from each other in a wafer substrate.
Another object of the present invention is to provide a die-separating process which prevents or at least minimizes cracking and/or chipping of die as the die are separated from each other in a wafer.
Still another object of the present invention is to provide a die-separating process which facilitates the absorption of vibrational energy imparted by a dicing saw in order to prevent or at least minimize cracking and/or chipping of the dies during the die separation process.
Yet another object of the present invention is to provide a die-separating process in which a single channel or all channels separating a die from other adjacent dies in a wafer are partially, rather than completely, cut through the wafer material in order to facilitate the absorption of vibrational dicing energy by the uncut wafer material during the die separation process and thereby prevent cracking and/or chipping of the die.
A still further object of the present invention is to provide a die-separating process which includes initially cutting partial separation channels through the wafer material along the X-axis scribe lines and then complete separation channels through the wafer material along the Y-axis scribe lines separating a die from adjacent dies in a wafer; cutting complete separation channels along the X-axis scribe lines and then partial separation channels along the Y-axis scribe lines; or cutting partial separation channels along the X-axis scribe lines followed by partial separation channels along the Y-axis scribe lines, in order to maintain sufficient thickness of wafer material between the adjacent dies to facilitate the absorption of saw blade-induced vibrational energy by the uncut wafer material during the die separation process.
Yet another object of the present invention is to provide a die-separating process which utilizes at least one set of partial separation channels cut in the wafer material along scribe lines separating each die from adjacent dies in a wafer, followed by application of roller pressure to the backside of the dies to complete separation of each die from the adjacent dies and prevent or at least minimize cracking or chipping of the dies due to saw-induced vibrational energy during the die separation process.